1. Field of the Invention
The field of the invention relates to memory devices and in particular to a memory formed of memory banks.
2. Description of the Prior Art
There is a desire for memory devices to have increased storage capacity, decreased power consumption and a decreased size. The individual semiconductor storage cells that form the memory devices and the input and output devices that allow access to them are not completely uniform and as the size of these devices decreases, this lack of uniformity increases. When designing a memory this lack of uniformity needs to be considered and the performance of the poorer components needs to be accounted for.
For example, with an SRAM memory, owing to a lack of uniformity in the bit cells and to possible offsets in the sense amplifiers sensing the signals in the bit cells, a voltage level that is greater than a level that most sense amplifiers would sense is chosen as a desired output level of a bit cell in order for it to safely provide a signal that the predicted worst sense amplifiers will be able to sense. FIG. 1 shows how a signal output from a bit cell varies with time. As can be seen from the different lines on this graph, that correspond to signals output by different bit cells, different sized signals are output by different cells, but they all increase with time. Thus, a delay time ΔT is provided between the bit cell being selected and the value being output, and this helps ensure that the value output by the cell will be sufficient to be detected by the sense amplifier. Thus, the length of this delay time is chosen so that the predicted worst cell in this set of cells will have reached a value required to trigger the worst sense amplifier that it is calculated is likely to be present. To estimate this, a statistical analysis of the performance of all the cells is performed. Once this delay time has been estimated it is input as the delay value in the delay circuit 12 in the memory cell 10, and this delays the data read signal that has been sent to the storage cell by ΔT before it is sent to the sense amplifier 14. Sense amplifier 14 then detects and outputs a signal read from the storage cell.
“A Replica Technique for Wordline and Sense Control in Low-Power SRAM” By Bharadwaj et al. IEE Journal of Solid State Circuits, Vol 33, No 8 August 1998 describes how these delays can be determined. “A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM” by Yap San Min et a. 4th IEEE International Symposium on Electronic Design, Test and Applications 2008, discloses a way of calculating the read timing margin of bit cells and a way of calculating the probability of meeting this constraint.
As memories become ever larger, the probability of cells with even worse characteristics occurring increases.
Furthermore, as memories become larger they are generally formed in banks that are individual memory arrays that are separately accessed. This is done to reduce RC delays which increase with the length of lines required to access individual storage cells within a large memory array.
Currently the delay time added between a request for data reaching a cell and a sense amplifier being enabled to detect and output the data is determined pessimistically to cover worst case predicted variations occurring in cells throughout the memory. It would be desirable to be able to improve the memory access so that a less pessimistic time could be used for at least some of the memory accesses.